This application claims priority to Korean Patent Application No. 2004-109280, filed on Dec. 21, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to fabrication of a field effect transistor having a buried gate pattern for affecting a threshold voltage of the field effect transistor.
2. Description of the Related Art
Semiconductor devices can largely be classified as memory devices and non-memory devices. A unit cell of most common semiconductor devices includes at least one field effect transistor, regardless of whether the semiconductor device is a memory device or a non-memory device. For achieving high integration or performance, a miniaturized field effect transistor having high performance is desired.
In the case of a DRAM (dynamic random access memory) device, a capacitor-less 1T (one transistor)-DRAM cell has been disclosed for increasing integration of the DRAM. The 1T-DRAM cell uses a floating body effect, storing data by accumulating carriers in the floating body and reading the data using the variation of threshold voltage according to the amount of stored carriers. The 1T-DRAM cell does not use a storage capacitor, thereby reducing the size of a unit cell and enabling a non-destructive read operation.
For example, a 1T-DRAM cell that uses a colliding ionization effect when writing has been disclosed in “Memory Design Using a One-Transistor Gain Cell on SOI” by T. Ohsawa, IEEE J. Solid-State Circuits, vol 37, no. 11, 2002, pp. 1510-1522. Also, a 1T-DRAM cell that uses a drain leakage current induced by a gate when writing has been disclosed in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) current for Low-power and High-speed Embedded Memory” by Ejji Yoshida, IEDM, 2003, pp. 913-916.
However, in such 1T-DRAM cells of the prior art, the source/drain regions directly contact the floating body in which carriers are accumulated. Thus, carriers may leak from the floating body when power is on or during reading, since a charge leakage path is formed at the contact points between the floating body and the source/drain regions.
On the other hand, a Programmable Read Only Memory (PROM) cell that includes a buried floating gate in a substrate has been disclosed in “Programmable Read Only Memory Cell and an Arrangement thereof, and a Method of Writing, Reading, and Erasing Information to/from the Memory Cells” by ‘INFINEON TECHNOLOGIES AG’ published in International Patent Application PCT/EP2002/009920. FIG. 1 is a cross-sectional view of a conventional PROM cell MC disclosed in that International Patent Application.
Referring to FIG. 1, a threshold voltage of a channel layer EPI is controlled according to the accumulation of charge in a floating gate FG of the PROM cell MC. A write operation in the PROM cell MC is performed by using tunneling of charge from the channel layer EPI through an insulating layer TOX.
However in the PROM cell MC, the bottom surface of the channel layer EPI contacts a substrate 10, which results in insufficient contact area between the floating gate FG and the channel layer EPI. As a result, the effect of controlling the threshold voltage with the floating gate FG is limited in the PROM cell MC. Also, as depicted in FIG. 1, the distance between the source/drain regions and a first diffusion region 22 is relatively short, potentially providing parasitic current paths through the source region S, the first diffusion region 22, and the drain region D.